1. Field of the Invention
The invention lies in integrated memory technology field. More specifically, the present invention relates to an integrated memory having first units of memory cells and second, redundant units of memory cells for replacing first units of memory cells, and to a method for repairing such an integrated memory.
Integrated memories generally have redundant memory cells for repairing defective memory cells. The redundant memory cells are connected to redundant row lines or redundant column lines, which can replace corresponding regular lines with defective memory cells in address terms. The integrated memory is thereby tested by an external test unit, for example, and the redundant elements are subsequently programmed using a so-called redundancy analysis. A redundancy circuit has programmable elements, for example in the form of programmable fuses, which serve for storing the address of a line to be replaced.
A memory module is tested and repaired in the course of the fabrication process, for example. For this purpose, the addresses of those tested memory cells which were detected as defective are stored in a so-called defect address memory of the test unit in order, in a subsequent step, to replace these memory cells by defect-free redundant memory cells using the stored addresses. In this case, the memory module is generally subjected to a plurality of tests. In this case, only those memory cells which pass all the tests are deemed to be functional or defect-free. If a memory cell does not pass one or more tests, then it is deemed to be defective and must be replaced by a defect-free redundant memory cell. In the case of integrated memories having a matrix-type memory cell array which has row lines and/or column lines, instead of an individual memory cell an entire row or column line is usually replaced by corresponding redundant row or column lines.
A principle object in the fabrication of integrated memories is to fabricate memories of specific size more cost-effectively, that is to say to minimize the fabrication costs per memory chip. A considerable part of the fabrication costs is allotted to the test costs associated with the memory test, which generally rise proportionally with the required test time per wafer on which the memory circuits are arranged. There is great interest, therefore, in minimizing the test time per wafer.
The test time per wafer is generally determined by the number of tests used per memory chip, the parallelism, that is to say the number of chips which are tested simultaneously, and also by the test speed. An upper limit is placed on increasing the parallelism and test speed, however, inter alia due to the finite size of the fail memory tester's defect address memory in the form of an SDRAM memory which stores the addresses of defective memory cells for the purpose of a subsequent repair analysis used by customary automatic test machines, and the upper limit is virtually always fully exhausted in the case of present-day memory sizes.
A memory repair is often effected in such a way that a plurality of redundant rows or columns are simultaneously used for the repair. The term used in this case is so-called clustering. A number of redundant rows or columns is programmed as an associated cluster for replacing one or more normal rows or columns. In this way, a repair element is produced with a cluster size corresponding to the number of redundant rows or columns. A repair element having the cluster size X then comprises X rows or columns. By way of example, if SC is the storage capacitance of the memory chip and CR and CS is the cluster size of the redundant row and column repair elements, respectively, then the following holds true for the size of the fail bitmap per memory chip
  f  =      S    ⁢                  ⁢          C      ·              1                  C          ⁢                                          ⁢          R                    ·              1                  C          ⁢                                          ⁢          S                    wherein case the fail bitmap of the memory chip can be compressed by the compression factor k=CR·CS in repair-compatible fashion.
For a given size of the fail bitmap per chip f and a given fail memory size F of the test system, the number of memory chips which can be tested simultaneously is at most F/f. On the other hand, the size of the fail bitmap per memory chip f depends on the compression factor k, as explained above. It is evident from this that an increase in the cluster size leads to lower f, thus to higher parallelism and thus finally to a shorter test time. In addition, however, increasing the compression factor k generally also implies a reduction of yield, since a larger cluster size given the same number of redundant rows or columns leads to a reduction of the number of redundant repair elements. By way of example, if there are 48 redundant rows available, then 24 row repair elements are obtained therefrom with a cluster size of 2, whereas only 12 row repair elements are obtained with a cluster size of 4. Such a situation is critical primarily in an early process stage of the fabrication process, where it is customary to use every redundant element in order to actually exceed a specific yield limit.